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AS7C1026B - 5V 64K x 16 CMOS SRAM

General Description

The AS7C1026B is a high-performance CMOS 1,048,576-bit Static Random Access Memory (SRAM) device organized as 65,536 words × 16 bits.

It is designed for memory applications where fast data access, low power, and simple interfacing are desired.

Key Features

  • Industrial and commercial versions.
  • Organization: 65,536 words × 16 bits.
  • Center power and ground pins for low noise.
  • High speed - 10/12/15/20 ns address access time - 5, 6, 7, 8 ns output enable access time.
  • Low power consumption: ACTIVE - 605 mW / max @ 10 ns.
  • TTL-compatible, three-state I/O.
  • JEDEC standard packaging.
  • ESD protection ≥ 2000 volts.
  • Latch-up current ≥ 200 mA - 44-pin 400 mil SOJ - 44-pin TSOP 2-400.

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Datasheet Details

Part number AS7C1026B
Manufacturer Alliance Semiconductor
File Size 110.12 KB
Description 5V 64K x 16 CMOS SRAM
Datasheet download datasheet AS7C1026B Datasheet

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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March 2004 ® AS7C1026B 5 V 64K X 16 CMOS SRAM Features • Industrial and commercial versions • Organization: 65,536 words × 16 bits • Center power and ground pins for low noise • High speed - 10/12/15/20 ns address access time - 5, 6, 7, 8 ns output enable access time • Low power consumption: ACTIVE - 605 mW / max @ 10 ns • TTL-compatible, three-state I/O • JEDEC standard packaging • ESD protection ≥ 2000 volts • Latch-up current ≥ 200 mA - 44-pin 400 mil SOJ - 44-pin TSOP 2-400 Pin arrangement 44-Pin SOJ (400 mil), TSOP 2 A4 A3 A2 A1 A0 CE I/O0 I/O1 I/O2 I/O3 VCC GND I/O4 I/O5 I/O6 I/O7 WE A15 A14 A13 A12 NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A5 A6 A7 OE UB LB I/O15 I/O14 I/O13 I/O12 GND VCC I/O11 I